Existing complementary metal oxide semiconductor (CMOS) memories consist of a large number of individual memory cells each storing an electrical charge corresponding to a digital 0 or a digital 1 state. The memory includes a number of cells each representing a plurality of multi-bit words. When a particular cell is read, a small voltage signal corresponding to the state of the cell is generated on a bit line connected to a sense amplifier (see FIG. 1). The sense amplifier discriminates between a small (lower) bit line output voltage representative of digital 0 state and a somewhat larger (higher) bit line voltage representative of a digital 1 state. High performance, high density CMOS static random access memories (SRAM) are preferably read at a very high speed to be compatible with the very high speed microprocessors. One of the greatest impediments to high speed performance results from the circuitry for amplifying a small analog array cell signal on a single bit line into a full swing digital signal. Further, one of the major problems presented for rapid readout of an analog signal is the time required to discriminate between a 0 signal and a 1 signal and the time to produce an output signal once the input signal has been properly discriminated.
Some existing sense amplifier designs require a large bit line voltage swing to properly trigger the state of the signal detection circuitry, thus increasing the memory access time. Other sense amplifier designs add large capacitive load to the bit line, hence slowing the signal development rate on the bit line. As a result, a significant period of time is required for a full sense signal to be generated, adding a substantial delay to the SRAM speed. Therefore, there is a need for a sense amplifier that exhibits low loading capacitance and facilitates higher speed sensing.
Disclosed herein in an exemplary embodiment is a sense amplifier for a memory device comprising: a first sensing stage comprising a first sensing device and a second sensing device operably connected to a first sense line and a second sense line respectively, to reduce the capacitive load on the first sense line and the second sense line. A source terminal of the sensing device is connected to a switchable current sink with drain terminal thereof connected to an input of a second sensing stage. The sense amplifier also includes a second sensing stage comprising cross-coupled inverters responsive to the first sensing stage, the second sensing stage is activated by a sense enable signal following a selected delay, and an output driver responsive to the second sensing stage.
Also disclosed herein in an exemplary embodiment is a sense amplifier for a memory device comprising: a first sensing stage comprising a first sensing device and a second sensing device operably connected to a first sense line and a second sense line, respectively, to reduce capacitive load on the first sense line and the second sense line. A source terminal of the sensing device is connected to a switchable current sink with drain terminal thereof connected to an input of a second sensing stage. The sense amplifier also includes: a second sensing stage comprising a pair of cross-coupled complementary inverters coupled to the switchable current sink, responsive to the first sensing stage and operably connected to the first sense line and the second sense line, the second sensing stage activated by a sense enable signal; and an output driver responsive to the second sensing stage.
Further disclosed herein in yet another exemplary embodiment is a method of detecting a signal on a pair of complementary sense lines in a dual-stage sense amplifier for a memory device comprising: detecting a differential voltage between a first sense line and a second sense line with a first sensing stage comprising a first sensing device and a second sensing device; amplifying said differential voltage with a second sensing stage comprising cross-coupled inverters responsive to the first sensing stage. The second sensing stage is activated by a sense enable signal following a selected delay, wherein the first sensing stage is deactivated once the second sensing stage is activated. The method also includes generating a output signal with an output driver responsive to the second sensing stage.
Also disclosed herein in yet another exemplary embodiment is a method of detecting a signal on a pair of complementary sense lines in a dual-stage sense amplifier for a memory device comprising: detecting a differential voltage between a first sense line and a second sense line with a first sensing stage comprising a first sensing device and a second sensing device; amplifying the differential voltage with a second sensing stage comprising cross-coupled inverters responsive to and in parallel with said first sensing stage, the second sensing stage activated by a sense enable signal. The method also includes generating a output signal with an output driver responsive to the second sensing stage.
These and other improvements are set forth in the following detailed description. For a better understanding of the invention with advantages and features, refer to the description and to the drawings.